Various lead finish options including solder (dipped or plated) are available for small outline (SO) surface mounted integrated circuits (IC's). These finishes have certain advantages and disadvantages. This paper will discuss the use of a thin, preplated palladium lead finish as an alternative to solder. Preplated leadframes offer the advantages of eliminating wet chemical processes on the encapsulated IC packages, as well as eliminating the mechanical handling associated with solder dipping or plating. Palladium plating was chosen as the external material for preplated leadframes after evaluation and examination of various alternatives. Palladium has an optimum mix of chemical and metallurgical properties for this application. Tests and experiments were performed which were designed to examine several key properties and behaviors of Pd as related to this application. These tests included: wetting characteristics, solder joint metallurgy, wire bonding, interaction with molding compounds, and electrochemical characteristics. Following initial feasibility studies, an extensive set of reliability and performance tests were run on a wide range of packaged integrated circuits. These included: operating life, temperature/humidity, thermal cycle/shock, lead finish performance and visual/mechanical tests. Texas Instruments (TI) and several customers jointly evalu-integrated circuits. These included: operating life, temperature/humidity, thermal cycle/shock, lead finish performance and visual/mechanical tests.
