DEGRADATION OF SUBMICRON N-CHANNEL MOSFET HOT-ELECTRON RELIABILITY DUE TO EDGE DAMAGE FROM POLYSILICON GATE PLASMA-ETCHING

被引：16

作者：

GU, T ^{[1
]}

AWADELKARIM, OO ^{[1
]}

FONASH, SJ ^{[1
]}

CHAN, YD ^{[1
]}

机构：

[1] ROCKWELL INT CORP,NEWPORT BEACH,CA 92658

来源：

IEEE ELECTRON DEVICE LETTERS | 1994年 / 15卷 / 10期

关键词：

D O I：

10.1109/55.320980

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The impact of poly-Si gate plasma etching on the hot electron reliability of submicron NMOS transistors has been explored. The results show that the gate oxide and SiO2-Si interface near the drain junction have a susceptibility to hot electron injection that increases with overetch time. We show for the first time that this degradation of hot electron reliability is attributable to the edge type of gate oxide damage resulting from direct plasma exposure during overetch processing. We demonstrate that this type of damage does not scale with channel length and becomes even more important in shorter channel transistors.

引用

页码：396 / 398

页数：3

共 14 条

[1]

CHEN ML, 1987, IEDM, P55

[2] A MODEL AND EXPERIMENTS FOR THIN OXIDE DAMAGE FROM WAFER CHARGING IN MAGNETRON PLASMAS [J].