A 3.0 V 40 MB/S HARD-DISK DRIVE READ CHANNEL IC

被引：4

作者：

DEVEIRMAN, GA ^{[1
]}

UEDA, S ^{[1
]}

CHENG, J ^{[1
]}

TAM, S ^{[1
]}

FUKAHORI, K ^{[1
]}

KURISU, M ^{[1
]}

SHINOZAKI, E ^{[1
]}

机构：

[1] SILICON SYST INC,NAKAHARA KU,KAWASAKI,KANAGAWA 211,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1995年 / 30卷 / 07期

关键词：

D O I：

10.1109/4.391118

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents a high performance low power BICMOS mixed signal ASIC that integrates all the electronics required by a hard disk drive (HDD) read channel, The IC includes the automatic gain control (AGC) circuit, a programmable continuous-time filter, two pulse qualifiers, the servo demodulator, the time base generator, the data synchronizer, and the encoder/decoder. Constant density recording with data rates between 14 and 40 Mb/s in 1,7 Run Length Limited (RLL) format and embedded 4-burst servo are supported, All the chip's specifications are guaranteed for supply voltages ranging from 3.0-5.5 V. Programming and testing are achieved via a 3-terminal bi-directional serial interface and internal registers, Nominal power dissipation at 3.0 V supply and 40 Mb/s data rate is 360 mW. Pulse pairing and write data jitter, two key performance parameters, each measured less than 300 ps.

引用

页码：788 / 799

页数：12