SUPERCHIP ARCHITECTURE FOR IMPLEMENTING LARGE INTEGRATED SYSTEMS

The paper introduces an architecture embodied in a large silicon chip, or 'superchip,' which can be tailored by the user to a specific system to perform a particular processing task. The methodology of system design using the superchip architecture is presented both at the top level of system organization and at a lower level of system customisation, through a suite of supporting software. The superchip architecture offers defect/fault tolerant capability and system reconfigurability by incorporating, as a key feature, a crossbar switching network in the system. This network connects all available processing elements in the superchip to achieve the required communication. Defect/fault tolerance is achieved by introducing redundancy through the switching network. The optimal redundancy predicted by yield models employed shows how a dramatic improvement over the yield without redundancy can be achieved. This brings the superchip yield up to an economically acceptable level, while keeping the hardware overhead at a minimum. An example is given to illustrate the design and customisation process for implementing an FFT system in the superchip style.