ANALYSIS OF LOAD STRUCTURES FOR CURRENT-MODE LOGIC

被引：2

作者：

ELMASRY, MI

THOMPSON, PM

机构：

[1] BELL NO RES,ELECTR DEVICES RES LAB,OTTAWA,ONTARIO,CANADA

[2] UNIV OTTAWA,DEPT ELECT ENGN,OTTAWA,ONTARIO,CANADA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1975年 / SC10卷 / 01期

关键词：

D O I：

10.1109/JSSC.1975.1050557

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：72 / 75

页数：4

共 12 条

[1]

BARNA A, 1969, IEEE J SOLI, VSC 4, P159

[2]

CAUGHEY M, 1972, TELESIS, V2, P17

[3]

CHUNG DH, 1963, IBM J JUL, P190

[4]

ECKTON WH, 1971, OCT INT EL DEV M

[5]

GIUCOLETTO LJ, 1966, IBM J JAN, P51

[6]

HERSHOWITZ GJ, 1968, COMPUTER AIDED INTEG, pCH3

[7]

KRUY JF, 1966, IEEE J SOLI, VSC 1, P81

[8] LATERAL COMPLEMENTARY TRANSISTOR STRUCTURE FOR SIMULTANEOUS FABRICATION OF FUNCTIONAL BLOCKS [J].

LIN, HC ;

FORMIGONI, N ;

VANDERLEK, B ;

TAN, TB ;

CHANG, GY .

PROCEEDINGS OF THE IEEE, 1964, 52 (12) :1491-+

[9] THEORY OF LATERAL TRANSISTORS [J].

LINDMAYER, J ;

SCHNEIDER, W .

SOLID-STATE ELECTRONICS, 1967, 10 (03) :225-+

[10]

LYNN DK, 1967, ANALYSIS DESIGN INTE

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