ELECTRICAL DESIGN OF A HIGH-SPEED COMPUTER PACKAGING SYSTEM

被引:10
作者
DAVIDSON, EE
机构
来源
IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY | 1983年 / 6卷 / 03期
关键词
D O I
10.1109/TCHMT.1983.1136188
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
引用
收藏
页码:272 / 282
页数:11
相关论文
共 8 条
[1]   3-DIMENSIONAL INDUCTANCE COMPUTATIONS WITH PARTIAL ELEMENT EQUIVALENT-CIRCUITS [J].
BRENNAN, PA ;
RAVER, N ;
RUEHLI, AE .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1979, 23 (06) :661-668
[2]  
Chang F. Y., 1978, Eleventh Annual Asilomar Conference on Circuits Systems and Computers, P29
[3]  
FELLER A, 1965, FAL AFIPS C P JOINT, V27, P511
[4]   TIMING ANALYSIS OF COMPUTER HARDWARE [J].
HITCHCOCK, RB ;
SMITH, GL ;
CHENG, DD .
IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1982, 26 (01) :100-105
[5]  
KATOPIS GA, 1979, 12TH P AS C, P500
[8]   ALGORITHMS FOR ASTAP - NETWORK ANALYSIS PROGRAM [J].
WEEKS, WT ;
JIMENEZ, AJ ;
MAHONEY, GW ;
MEHTA, D ;
QASSEMZADEH, H ;
SCOTT, TR .
IEEE TRANSACTIONS ON CIRCUIT THEORY, 1973, CT20 (06) :628-634