1.5-MUM CMOS GATE ARRAYS WITH ANALOG DIGITAL MACROS DESIGNED USING COMMON BASE ARRAYS

被引:6
作者
KAWADA, S
HARA, Y
ISONO, T
INUZUKA, T
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D O I
10.1109/4.34081
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
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页码:985 / 990
页数:6
相关论文
共 7 条
[1]  
Gregorian R., 1986, ANALOG MOS INTEGRATE, P505
[2]   ANALOG FUNCTIONS IMPLEMENTED ON DIGITAL CMOS GATE ARRAYS - MERITS AND PROBLEMS [J].
HAGELAUER, R ;
RONGE, K .
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, 1986, 33 (04) :371-376
[3]  
KASH R, 1981, ELECTRONICS, P109
[4]  
KATO H, 1983 P IEEE CUST INT, P19
[5]  
MAEDING DG, 1985 P IEEE CUST INT, P491
[6]   HIGH-PERFORMANCE DESIGNS WITH CMOS ANALOG STANDARD CELLS [J].
PLETERSEK, T ;
TRONTELJ, J ;
TRONTELJ, L ;
JONES, J ;
SHENTON, G .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (02) :215-222
[7]   ANALOG CMOS BUILDING-BLOCKS FOR CUSTOM AND SEMICUSTOM APPLICATIONS [J].
STONE, DC ;
SCHROEDER, JE ;
KAPLAN, RH ;
SMITH, AR .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1984, 19 (01) :55-61