THE POWERPC 601-MICROPROCESSOR

被引：9

作者：

BECKER, MC ^{[1
]}

ALLEN, MS ^{[1
]}

MOORE, CR ^{[1
]}

MUHICH, JS ^{[1
]}

TUTTLE, DP ^{[1
]}

机构：

[1] IBM CORP,DIV ADV WORKSTN & SYST,AUSTIN,TX 78759

来源：

IEEE MICRO | 1993年 / 13卷 / 05期

关键词：

D O I：

10.1109/40.238002

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The PowerPC 601 microprocessor is the first of a family of processors based on the PowerPC architecture. The general-purpose processor contains a 32-Kbyte cache and a superscalar machine organization that allows dispatch and execution of up to three instructions each clock cycle. The bus interface and storage control mechanism can be configured for a wide range of system designs: low-cost desktop personal computers to high-performance multiprocessor systems.

引用

页码：54 / 68

页数：15

共 10 条

[1]

ALLEN M, 1993, FEB P COMPC, P117

[2]

DIEFENDORFF K, 1992, IEEE MICRO, V12, P40, DOI 10.1109/40.127582

[3]

MOORE CR, 1992, OCT P INT C COMP DES

[4]

MOORE CR, 1993, FEB P COMPC, P109

[5] IBM RISC SYSTEM-6000 PROCESSOR ARCHITECTURE [J].

OEHLER, RR ;

GROVES, RD .

IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 1990, 34 (01) :23-36

[6]

SILHA E, 1993, FEB P IEEE COMPCON, P104

[7]

1985, ANSIIEEE7541985

[8]

1993, PCL LOCAL BUS SPECIF

[9]

1989, 802P8961D802 DRAFT

[10]

1990, IEEE11491 STD

← 1 →