SIMULATION TECHNIQUES FOR MIXED ANALOG DIGITAL CIRCUITS

被引:18
作者
ACUNA, EL
DERVENIS, JP
PAGONES, AJ
YANG, FL
SALEH, RA
机构
[1] Coordinated, Science Laboratory, University of Illinois, Urbana, IL
[2] Coordinated Science Laboratory, Univer, sity of Illinois, IBM Corporation, Urbana, East, Fishkill, IL
[3] Coordinated Science Laboratory University, of Illinois, Development Center, Motorola, Inc., Corporate Research and, Urbana, Schaumburg, IL
基金
美国国家科学基金会;
关键词
Data Conversion; Analog to Digital - Logic Circuits - Semiconductor Devices; MOS;
D O I
10.1109/4.52156
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper describes the techniques used in a new Simulator called iSPLICE3 for the analysis of mixed analog/digital circuits. iSPLICE3 combines circuit, switch-level timing, and logic simulation modes using event-driven selective-trace techniques. It also uses a hierarchical schematic capture package called iSPI (Simulation Program Interface) for design entry, circuit partitioning, and simulation control. The novel contributions in this paper include a new de solution method, a mixed-mode interface modeling technique, and an automatic partitioning approach for MOS logic circuits. The details of these three methods are provided in this paper, along with the architecture and transient simulation algorithms used in iSPLICE3. In addition, the results of circuit simulations and mixed-mode simulations of a CMOS static RAM, two A/D converters, and a phase-locked loop are presented. These results indicate that iSPLICE3 is between one and two orders of magnitude faster than SPICE2 with negligible loss in accuracy. 0018-9200/90/0400-0353$01.00 © 1990 IEEE
引用
收藏
页码:353 / 363
页数:11
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