HYBRID DRY WET CHEMICAL ETCHING PROCESS FOR VIAHOLES FOR GALLIUM-ARSENIDE MMIC MANUFACTURING

被引:5
作者
CHANG, EY
NAGARAJAN, RM
KRYZAK, CJ
PANDE, KP
机构
[1] Unisys Corp, St Paul, MN, USA
关键词
INTEGRATED CIRCUITS -- Etching;
D O I
10.1109/66.17990
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Using the wafer via-hole connections for monolithic microwave integrated circuits (MMICs), a manufacturing technique has been developed by combining reactive-ion etching (RIE) and wet-chemical-spray etching processes for 100-μm gallium arsenide wafers. The dry process is based on the use of SiCl4-BCl3-Cl 2 and BCl3-Cl2 gas mixtures at room temperature in a reactive ion etcher. The etching parameters are optimized for initial anisotropic etching, followed by slightly isotropic etching. Dynamic wet-chemical-spray etching based on H3PO4-H2O2-H2O at 45°C is used to remove the residual lip and surface roughness following reactive ion etching. The combined dry-wet etching approach was used to fabricate 95% have been achieved across a 3-inch wafers. Metallized via-hole contacts to power FET chips show a contact resistance <20 mΩ per via for 5-μm selective gold plating.
引用
收藏
页码:157 / 159
页数:3
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