A NEW PLL FREQUENCY-SYNTHESIZER WITH HIGH SWITCHING SPEED

被引:32
作者
KAJIWARA, A [1 ]
NAKAGAWA, M [1 ]
机构
[1] KEIO UNIV,DEPT ELECT ENGN,KOHO KU,YOKOHAMA,JAPAN
关键词
Cellular radio systems - Control - Digital signal processing - Mathematical models - Performance - Phase control - Phase locked loops - Switching - Telecommunication networks - Variable frequency oscillators - Voice/data communication systems;
D O I
10.1109/25.182591
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this paper, a new phase-locked loop (PLL) frequency synthesizer with high switching speed is proposed, and the experimental and theoretical results are given. Mobile communication networks are evolving towards micro cellulars operating in narrowband TDMA and microwave bands to meet the rapidly increasing demands for both voice and data services. Therefore, synthesizers with high switching speed are required for the realization. However, it will be difficult for conventional synthesizers to provide the switching time of shorter than 1 ms. The PLL synthesizer proposed here is composed entirely of digital signal processors except for a voltage-controlled oscillator (VCO). The VCO control signal is derived by the subtraction of the linear reference phase and the feedback phase, therefore, it does not need the band-limited loop filter which limits the ability of the loop to switch fast. The experimental results show that it can provide switching time as short as 0.1 ms, which is 10(2) is similar to 10(3) times higher than conventional PLL synthesizers, and spurs of less than -60 dB.
引用
收藏
页码:407 / 413
页数:7
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