A 3-D SIDEWALL FLASH EPROM CELL AND MEMORY ARRAY

被引：12

作者：

PEIN, H ^{[1
]}

PLUMMER, JD ^{[1
]}

机构：

[1] STANFORD UNIV,CTR INTEGRATED SYST,STANFORD,CA 94305

来源：

IEEE ELECTRON DEVICE LETTERS | 1993年 / 14卷 / 08期

关键词：

D O I：

10.1109/55.225597

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A promising new 3-D sidewall flash EPROM cell has been implemented in a novel memory array. The sidewall cell is a single-transistor stacked gate cell built on the sidewalls of a silicon pillar. The gates surround the pillar and current flows vertically from top to bottom of the pillar. The cell size approaches the square of the minimum pitch and is less than 40% of the conventional NOR-type structure. The cell and array architecture promise to be highly scalable.

引用

页码：415 / 417

页数：3