PARASITIC-COMPENSATED SWITCHED-CAPACITOR DELAY-LINES

被引:7
作者
DIAS, VF [1 ]
FRANCA, JE [1 ]
机构
[1] INST SUPER TECN, DEPT ENGN ELECTROTECN & COMP, P-1096 LISBOA, PORTUGAL
关键词
D O I
10.1049/el:19880255
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
引用
收藏
页码:377 / 379
页数:3
相关论文
共 5 条
[1]   OPTIMUM DESIGN OF FIR SWITCHED-CAPACITOR DECIMATORS USING LOW-GAIN AMPLIFIERS [J].
DIAS, VF ;
FRANCA, JE .
ELECTRONICS LETTERS, 1988, 24 (04) :195-197
[2]   PARASITIC COMPENSATED SWITCHED CAPACITOR CIRCUITS [J].
FLEISCHER, PE ;
GANESAN, A ;
LAKER, KR .
ELECTRONICS LETTERS, 1981, 17 (24) :929-931
[3]  
FRANCA JE, 1985, IEEE T CAS, V32, P877
[4]  
FRANCA JE, IN PRESS IEEE T CIRC
[5]  
HASLER M, 1981, P IEEE INT S CIRCUIT, P42