NORA - A RACEFREE DYNAMIC CMOS TECHNIQUE FOR PIPELINED LOGIC STRUCTURES

被引:155
作者
GONCALVES, NF
DEMAN, HJ
机构
关键词
D O I
10.1109/JSSC.1983.1051937
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
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页码:261 / 266
页数:6
相关论文
共 8 条
  • [1] DEMAN H, 1982, P IEEE INT C CIRCUIT, P42
  • [2] GONCALVES NF, 1982, SEP ESSCIRC, P141
  • [3] HIGH-SPEED PROGRAMMABLE LOGIC-ARRAYS IN ESFI SOS TECHNOLOGY
    HEBENSTREIT, E
    HORNINGER, K
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1976, 11 (03) : 370 - 374
  • [4] HIGH-SPEED COMPACT CIRCUITS WITH CMOS
    KRAMBECK, RH
    LEE, CM
    LAW, HFS
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1982, 17 (03) : 614 - 619
  • [5] Pensey W. M., 1972, MOS INTEGRATED CIRCU, P260
  • [6] SHOJI M, 1982, P IEEE INT C CIRCUIT, P112
  • [7] HIGH-DENSITY CMOS ROM ARRAYS
    STEWART, RG
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1977, 12 (05) : 502 - 506
  • [8] CLOCKED CMOS CALCULATOR CIRCUITRY
    SUZUKI, Y
    ODAGAWA, K
    ABE, T
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1973, SC-8 (06) : 462 - 469