REALISTIC STATISTICAL WORST-CASE SIMULATIONS OF VLSI CIRCUITS

A simple and cost-effective method for evaluating the parametric product manufacturability of VLSI circuits is presented. The method, named Gradient Analysis, enables designers to predict the standard deviation of the circuit performance from measured or specified design parameter variations. This method, with a minimum extra design cost, avoids the overdesign associated with the traditional prediction of the worst-worst-case performance of VLSI circuits. Gradient Analysis also provides designers with information on the sensitivity of the circuit performance variations to the design parameter variations. In this way the key design parameters for process monitoring and control are identified. Experimental qualification of the method is discussed based on development and production data of VLSI products such as high-speed 1.2-mu-m 64 K CMOS SRAM's.