DIGRAPH RELAXATION FOR TWO-DIMENSIONAL PLACEMENT OF IC BLOCKS

被引：6

作者：

CIESIELSKI, MJ ^{[1
]}

KINNEN, E ^{[1
]}

机构：

[1] UNIV ROCHESTER,DEPT ELECT ENGN,ROCHESTER,NY 14627

来源：

关键词：

D O I：

10.1109/TCAD.1987.1270246

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

INTEGRATED CIRCUITS

引用

页码：55 / 66

页数：12

共 15 条

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CIESIELSKI, MJ .

[3]

CIESIELSKI MJ, 1983, THESIS U ROCHESTER

[4]

ELGAMAL AA, 1981, IEEE T CAS I, P888

[5]

HASSETT JE, 1982, 19TH P DES AUT C, P777

[6] GRAPH-OPTIMIZATION TECHNIQUES FOR IC LAYOUT AND COMPACTION [J].

KEDEM, G ;

WATANABE, H .

[7]

Lauther U., 1979, 16th design automation conference proceedings, P1, DOI 10.1109/DAC.1979.1600080

[8]

OHTSUKI T, 1970, SEP P ICCST KYOT, P67

[9]

OTTEN RHJ, 1975, P IEEE INT S CIRCUIT, P231

[10]

PREAS BT, 1978, 15TH P DES AUT C LAS, P206