LOW-CONDUCTANCE DRAIN (LCD) DESIGN OF INALAS/INGAAS/INP HEMTS

被引：8

作者：

PAO, YC ^{[1
]}

HARRIS, JS ^{[1
]}

机构：

[1] STANFORD UNIV,DEPT ELECT ENGN,STANFORD,CA 94305

来源：

IEEE ELECTRON DEVICE LETTERS | 1992年 / 13卷 / 10期

关键词：

D O I：

10.1109/55.192824

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The concepts of the low-conductance drain (LCD) design approach for lattice-matched InAlAs/InGaAs/InP HEMT's are demonstrated for improved device performance. The trade-off for LCD HEMT characteristics is a tapered current gain cutoff frequency f(t) under high drain-to-source bias. This behavior is, in principle, due to the fact that the LCD approach increases the effective gate length of the HEMT's in exchange for reduced peak channel electric field. Two-dimensional PISCES simulation was used to optimize the improvements while simultaneously minimizing this undesirable effect for a LCD HEMT structure.

引用

页码：535 / 537

页数：3

共 7 条

[1] INALAS/INGAAS/INP HEMTS WITH HIGH BREAKDOWN VOLTAGES USING DOUBLE-RECESS GATE PROCESS [J].