BOUNDARY-SCAN DESIGN PRINCIPLES FOR EFFICIENT LSSD ASIC TESTING

被引：12

作者：

BASSETT, RW ^{[1
]}

TURNER, ME ^{[1
]}

PANNER, JH ^{[1
]}

GILLIS, PS ^{[1
]}

OAKLAND, SF ^{[1
]}

STOUT, DW ^{[1
]}

机构：

[1] IBM CORP,DIV GEN TECHNOL,ESSEX JUNCTION,VT 05452

来源：

IBM JOURNAL OF RESEARCH AND DEVELOPMENT | 1990年 / 34卷 / 2-3期

关键词：

D O I：

10.1147/rd.342.0339

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A boundary-scan logic design method that depends only on level-sensitive scan design (LSSD) principles has been developed for IBM CMOS application-specific integrated circuit (ASIC) products. This technique permits comprehensive testing of LSSD ASICs with high signal input/output (I/O) pin counts, using relatively inexpensive reduced-pin-count automatic test equipment (ATE). This paper describes the LSSD logic structures required, the reduced-pin-count testing and burn-in processes used, and the ASIC product design decisions that must be made to establish a consistent boundary-scan implementation.

引用

页码：339 / 354

页数：16