DELAY ANALYSIS OF SERIES-CONNECTED MOSFET CIRCUITS

CMOS gate delay is analyzed using a new realistic short-channel MOS model. Closed-form delay formulas are obtained for CMOS inverters and series-connected MOSFET structures (SCMS's), which include short-channel effects. It is shown that the ratio of the delay of NAND/NOR to the delay of inverter becomes smaller in the submicrometer region. This is because the V(DS) and V(GS) of each MOSFET in the SCMS are smaller than those of an inverter MOSFET. The smaller voltages in turn mitigate and relax the severe carrier velocity saturation in miniaturized MOSFET's. This result encourages more extensive use of NAND/NOR/complex gates, cascode voltage switch logic [1], and hot-carrier resistant logic [2] in the submicrometer circuit design. The results of the analysis are informative for submicrometer VLSI designs. For example, if the maximum number of series-connected MOSFET's was considered to be five in 2-mu-m designs, then the number can be increased to six or seven in the submicrometer circuit design. In the typical cases in VLSI designs, the delay ratio for N-SCMS is much less than N2. The delay dependence on input terminal position for SCMS structures is also described.