TIME-DOMAIN MACROMODELS FOR VLSI INTERCONNECT ANALYSIS

被引：44

作者：

KIM, SY ^{[1
]}

GOPAL, N ^{[1
]}

PILLAGE, LT ^{[1
]}

机构：

[1] UNIV TEXAS,DEPT ELECT & COMP ENGN,AUSTIN,TX 78712

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1994年 / 13卷 / 10期

基金：

美国国家科学基金会;

关键词：

D O I：

10.1109/43.317469

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a method of obtaining time-domain macromodels of VLSI interconnection networks for circuit simulation. The goal of this work is to include interconnect parasitics in a circuit simulation as efficiently as possible, without significantly compromising accuracy. Stability issues and enhancements to incorporate transmission line interconnects are also discussed. A unified circuit simulation framework, incorporating different classes of interconnects and based on the proposed macromodels, is described. The simplicity and generality of the macromodels is demonstrated through examples employing RC- and RLC-interconnects.

引用

页码：1257 / 1270

页数：14