Clock buffer chip with multiple target automatic skew compensation

被引：18

作者：

Watson, RB ^{[1
]}

Iknaian, RB ^{[1
]}

机构：

[1] DIGITAL EQUIPMENT CORP,ALPHA SERVER GRP,MAYNARD,MA 01754

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1995年 / 30卷 / 11期

关键词：

D O I：

10.1109/4.475715

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes the application of a digital delay locked loop that compensates for variable delays on the clock chip, printed circuit board clock traces, and the clock systems on multiple ASIC's, For a computer system consisting of nine PC boards (''modules'') plugged into a back plane with two clock chips per board and six ASIC's per clock chip, a locking range of 25-150 MHz was achieved with a maximum skew in the system of less than 1 ns.

引用

页码：1267 / 1276

页数：10