DESIGN OF A 100-MHZ 10-MW 3-V SAMPLE-AND-HOLD AMPLIFIER IN DIGITAL BIPOLAR TECHNOLOGY

This paper describes the design of an all-npn open-loop sample-and-hold amplifier intended for use at the front end of analog-to-digital converters, Configured as a quasidifferential topology, the circuit employs capacitive coupling between the input and output to achieve differential voltage swings of 3 V in a 3.3-V system, It also exploits the high speed of bipolar transistors to attain a sampling rate of 100 MHz with a power dissipation of 10 mW. A prototype fabricated in a 1.5-mu m 12-GHz digital bipolar technology exhibits harmonics 60 dB below the fundamental with a 10-MHz sinusoidal input, The hold-mode feedthrough is less than -60 dB and the droop rate is 100 mu V/ns.