OPTIMAL MULTIPROCESSOR TASK-SCHEDULING USING DOMINANCE AND EQUIVALENCE-RELATIONS

被引:3
作者
CHOU, HC [1 ]
CHUNG, CP [1 ]
机构
[1] NATL CHIAO TUNG UNIV,INST COMP SCI & INFORMAT ENGN,HSINCHU 30050,TAIWAN
关键词
D O I
10.1016/0305-0548(94)90033-7
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
We propose an optimization scheme for unit-execution-time task scheduling on multiprocessors. In this scheme, dominance, semi-dominance, equivalence and semi-equivalence relations between tasks are first defined. The solution tree technique is adopted to keep track of the unfinished sub-schedules. We prove that when certain conditions are satisfied, a sub-schedule need not be explored further, since it cannot lead to a schedule better than some others. An algorithm that avoids generating such non-optimal schedules is presented. Then we conduct experiments to show the promise of our scheme in reducing solution space. Another advantage of this scheme is its extensibility. This scheme can easily be applied to other scheduling problems by simply adding additional constraints to the original definitions of the dominance, semi-dominance, equivalence and semi-equivalence relations.
引用
收藏
页码:463 / 475
页数:13
相关论文
共 9 条
[1]  
Hu, Parallel sequencing and assembly line problems, Operations Research, 9, pp. 841-848, (1961)
[2]  
Coffman, Graham, Optimal scheduling for two-processor system, Acta Inform., 1, pp. 200-213, (1972)
[3]  
Garey, Johnson, Computers and Intractability: A Guide to the Theory of NP-Completeness, (1979)
[4]  
Ramamoorthy, Chandy, Gonzalez, Optimal scheduling strategies in a multiprocessor system, IEEE Transactions on Computers, 21, pp. 137-146, (1972)
[5]  
Cheng, Sin, A state-of-the-art review of parallal-machine scheduling research, Eur. J. opl Res., 47, pp. 271-292, (1990)
[6]  
Edward, Jurg, Narsingh, Combinatioral Algorithms: Theory and Practice, (1977)
[7]  
Bernstein, Gertner, Scheduling expressions on a pipelined processor with a maximal delay of one cycle, J. ACM trans. program lang. Syst., 11, pp. 57-66, (1989)
[8]  
Warren, Instruction scheduling for the IBM RISC system/6000 processor, IBM J. res. Devl., 34, pp. 85-92, (1990)
[9]  
Lam, Sethi, Worst case analysis of two scheduling algorithm, SIAM Journal on Computing, 6, pp. 518-536, (1977)