HIGH-SPEED ANALOG CMOS PIPELINE SYSTEM

We present a switched-capacitor readout system for high speed analog signals. It consists of a 10 MHz four-channel delay-line chip with 58 samples per channel and a 12 channel buffer chip with a sampling rate of 1 MHz and a depth of nine samples. In addition the buffer chip includes an analog multiplexer with 25 inputs for the buffer channels and for 13 additional unbuffered signals. Both chips have been fabricated in CMOS-technology and will be used for the readout of the ZEUS high resolution calorimeter. The circuit and chip concept will be presented and some design optimizations will be discussed. Measurements from integrated prototypes will be given including some experimental data from irradiated chips. © 1990.