A 10-B 75-MSPS SUBRANGING A/D CONVERTER WITH INTEGRATED SAMPLE AND HOLD

This paper introduces the design of a fully differential two-step A/D converter. A new sample-and-hold (S/H) circuit based on a unity-gain feedback amplifier, flash ADC's driven by differential resistor ladders, and a differential DAC combined with the subtractor are described. The chip has been fabricated in a standard high-speed bipolar process and, by extensively utilizing compensation techniques, achieves ± 1 LSB integral nonlinearity and low harmonic distortions. A 75 megasample-per-second (MSPS) conversion rate, not yet exceeded even by full-flash 10-b ADC's, has been achieved with a power consumption of 2 W. Due to the S/H circuit, the input bandwidth is 250 MHz; the effective resolution of 9 b at 5 MHz exhibits a gradual decrease over input frequency, but still remains above 8 b up to 50 MHz. © 1990 IEEE