A SELF-LEARNING NEURAL NETWORK CHIP WITH 125 NEURONS AND 10K SELF-ORGANIZATION SYNAPSES

被引：13

作者：

ARIMA, Y ^{[1
]}

MASHIKO, K ^{[1
]}

OKADA, K ^{[1
]}

YAMADA, T ^{[1
]}

MAEDA, A ^{[1
]}

KONDOH, H ^{[1
]}

KAYANO, S ^{[1
]}

机构：

[1] MITSUBISHI ELECTR CO,LSI RES & DEV LAB,DEPT VLSI DEVICE DEV 1,ITAMI,HYOGO 664,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1991年 / 26卷 / 04期

关键词：

D O I：

10.1109/4.75062

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes an on-chip learning neural network LSI. The chip integrates 125 neuron units and 10K synapse units with the 1.0-mu-m double-poly-Si, double-metal CMOS technology. Most of this integration has been realized by employing the mixed design architecture of digital and analog circuits. The fully feedback connection network LSI can memorize at least 15 patterns with 50-mu-s learning time for each pattern. Under the condition that each test vector keeps a Hamming distance of 6 from memorized pattern, a correct association rate of 98% is obtained. The relaxation time is 1 to 2-mu-s. This chip consumes less than 1.5 W.

引用

页码：607 / 611

页数：5