32X32 SHARED BUFFER TYPE ATM SWITCH VLSIS FOR B-ISDNS

This paper describes a set of 0.8-mu-m CMOS VLSI's developed for shared buffer switches in ATM switching systems. A unit switch, of which the size is 32 x 32, consists of eight buffer memory VLSI's (BFM-VLSI's), two memory control VLSI's (CTRL-VLSI's), and two commercially available FIFO memory LSI's. Using the VLSI's, the 32 x 32 switch can be mounted on a printed board. This switch is a shared buff er switch. It achieves buffer memory utilization improvement through the use of buffer sharing among all output ports of the switch and has a large 2 Mb shared buff er which can save 4096 cells. As a result, this switch can satisfy the cell loss rate requirements, not only under random traffic conditions but also under burst traffic conditions. The switch has a priority control function to meet the requirements for various media. The switch can have a multicast function by adding multicast circuits to the developed VLSI's. A 600 Mb/s link switch can be achieved by modifying the CTRL-VLSI and by adding some circuits without redesigning the BFM-VLSI. These functions are useful for multimedia ATM networks. Using eight 32 x 32 switching boards, a complete nonblocking 64 x 64 switch can be achieved with a matrix-switching-network expansion method. A three-stage switching network consists of a 1024 x 1024 switch using 96 switching boards which have 32 input-output ports. In this network, the ATM bandwidth allocation of the call setup cannot be realized very frequently due to an inner link blocking even if the bandwidth on an input line and an output line can be allocated. However, a nonblocking switching network can be achieved using higher transmission-rate internal links in relation to the incoming lines.