NOVEL PIPELINED SERIAL PARALLEL MULTIPLIER

被引：11

作者：

AITBOUDAOUD, D

IBRAHIM, MK

HAYESGILL, BR

机构：

[1] Department of Electrical and Electronic Engineering, University of Nottingham, Nottingham

来源：

ELECTRONICS LETTERS | 1990年 / 26卷 / 09期

关键词：

Circuit theory and design; Digital circuits;

D O I：

10.1049/el:19900381

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A novel unidirectional pipelined serial/parallel multiplier (PSPM) is presented. This design has halves the initial delay and reduces the number of latches by 10% of the conventional structure. An area-time criteria is used to compare the new architecture with the old PSPM. © 1990, The Institution of Electrical Engineers. All rights reserved.

引用

页码：582 / 583

页数：2