PHYSICAL PHENOMENA AND LIMITATIONS IN SUBMICROMETER MOSFETS

被引：2

作者：

DIKE, RSU

机构：

[1] Department of Electrical/Electronic Engineering, Federal University of Technology, Owerri, PMB 1526, Imo state

来源：

INTERNATIONAL JOURNAL OF ELECTRONICS | 1994年 / 76卷 / 03期

关键词：

D O I：

10.1080/00207219408925936

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In the drive towards greater integration as occasioned by VLSI, MOS device dimensions and technology are scaled down appropriately into the submicron range. This paper analyses the physical and technological limitations for MOS VLSI arising from down-scaling. Specifically, drain-induced barrier lowering, velocity saturation and subthreshold temperature sensitivity effects are examined quantitatively. The results suggest that there may well be a minimum useful size beyond which scaling may not yield strong improvements of device performance.

引用

页码：403 / 415

页数：13

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