Margins and Yield in Single Flux Quantum Logic

Simulations are used to optimize the design of simple rapid single flux quantum (RSFQ) logic gates and to determine their margins. Optimizations based on maximizing the smallest (critical) margin result in critical margins in the range of 19-50%. A Monte Carlo approach is used to illustrate the relationship between margins and process yield. Based on single gate simulations, the results show that 1-sigma parameter spreads of less than about 5% will be required to make medium or large scale integrated RSFQ logic circuits. Finally, a single-bit full adder using five RSFQ gates and a local self-timing network is simulated with discrete components. The full adder used 2000 A/cm(2) junctions with a specific capacitance of 0.04 pF/mu m(2) and had a logic delay of 87 ps and a worst-case margin of +/- 19%. A small margin reduction results from loading which is not present in the individual gate simulations.