APPLICATION-SPECIFIC ARCHITECTURAL METHODOLOGIES FOR HIGH-THROUGHPUT DIGITAL SIGNAL AND IMAGE-PROCESSING

The VLSI integration of DSP applications in many frontend and medium-level video, imaging, and radar systems requires relatively high throughputs (10-100 MHz). As a result, this leaves little room for hardware multiplexing. Usually separate (hit-sliced) hardware resources have to be implemented for every operator in the algorithmic flowgraph. In this paper, architectural strategies are discussed for this class of high-speed applications. In principle, they can be classified between the two extremes of cooperating multiplexed data paths and regular arrays which adopt hard-wired control flow with low hardware sharing. In addition, we have investigated architectures exploiting large hardware-sharing ratios which are more suited for the back-end modules in the target DSP systems. Realistic test vehicles are discussed in order to evaluate the alternatives. Moreover, guidelines have been extracted to select such an ASIC architecture. These are dependent on the required throughput, the structure of the algorithm, and the corresponding signal flowgraph. © 1990 IEEE