SAR - FAST COMPUTER FOR CAMAC DATA ACQUISITION

被引：8

作者：

BRICAUD, B

FAIVRE, JC

PAIN, J

机构：

[1] CEN Saclay, BP 2

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 1979年 / 26卷 / 04期

关键词：

D O I：

10.1109/TNS.1979.4330183

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An original 32-bit computer architecture has been designed, based on bit-slice microprocessors. Around the AMD 2901, a 32 bit instruction set was defined with a 200 ns execution time per instruction Basic memory capacity is equally divided in two 32K-32 bit zones named Program memory and Data memory. The computer has a Camac Branch interface; during aCamac transfer activation, which lasts seven cycles, five cycles are free for processing. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.

引用

页码：4641 / 4644

页数：4