SPARCLE - AN EVOLUTIONARY PROCESSOR DESIGN FOR LARGE-SCALE MULTIPROCESSORS

被引：46

作者：

AGARWAL, A

KUBIATOWICZ, J

KRANZ, D

LIM, BH

YEUNG, D

DSOUZA, G

PARKIN, M

机构：

[1] MIT,COMP SCI LAB,545 TECHNOL SQ,CAMBRIDGE,MA 02139

[2] LSI LOG,SPARC SYST DIV,MILPITAS,CA

[3] LSI LOG,COREWARE GRP,MILPITAS,CA

[4] MIT,DEPT ELECT & COMP ENGN,CAMBRIDGE,MA 02139

[5] MIT,DEPT ELECT ENGN & COMP SCI,CAMBRIDGE,MA 02139

来源：

IEEE MICRO | 1993年 / 13卷 / 03期

基金：

美国国家科学基金会;

关键词：

D O I：

10.1109/40.216748

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Working jointly at MIT, LSI Logic, and Sun Microsystems, designers created the sparcle processing chip by evolving an existing RISC architecture toward a processor suited for large-scale multiprocessors. This chip supports three multiprocessor mechanisms: fast context switching, fast, user-level message handling, and fine-grain synchronization. The Sparcle effort demonstrates that RISC architectures coupled with a communications and memory management unit do not require major architectural changes to support multiprocessing efficiently.

引用

页码：48 / 61

页数：14

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