MONOLITHIC CHARGE-BALANCING SUCCESSIVE APPROXIMATION A-D TECHNIQUE

A new multiple-differential-voltage input, MOS, sampled-data, “charge-balance” comparator which can “weight” or scale each of many input voltage pairs has been developed. This comparator easily allows a differential analog input voltage capability on a monolithic A/D converter and greatly reduces the required number of resistors and decoding switches of a potentiometric successive approximation register (SAR) A/D design. An 8 bit converter has been built which uses 20 R's and 32 switches as compared to the 256 R's and 512 switches of a standard 2NR ladder design. Measurements made on the 8 bit A/D converter are reported and indicate that at least 12 bit converters are possible with this technique. Therefore, a 13 bit converter has been designed which exhibits even greater component reductions-33 R's and 64 switches instead of 8192 R's and 16384 switches. A simple interface to microprocessors is provided for both converters which makes use of the standard logic signals of the control bus where the A/D is designed to appear as memory or an I/O port to the microprocessor. A new flexible reference voltage circuit is presented which, in combination with the analog differential input voltage feature, can accommodate arbitrary analog input voltage spans with any desired zero scale offset. The calibration problems of the 13 bit design are handled by making use of an on-chip laser-trimmable ROM (LROM) which stores and inserts the proper correction “charge” into the comparator as a function of the dynamic digital codes in the SAR latch. This is easily electrically overdriven at wafer sort and the corrections which are found to be needed are then permanently programmed by laser-cut, silicon-chromium, thin-film, digital programming links. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.