HALL EFFECT IN SILICON-CHROMIUM FILMS

Hall effect and resistivity of sputtered silicon-chromium films have been measured versus temperature between -200°and +500°C on samples annealed at 550°C for 10 min. The films were dc diode sputtered at 1.0 and 2.5 kV from cathodes containing 17, 25, and 33 at.% Cr. The results are interpreted in terms of a one-carrier conduction process, the positive Hall voltage indicating holes. The effective hole concentration p = 1/RHq at room temperature is about 3×1021 cm-3 and is nearly independent of composition and sputtering voltage; it increases slightly with increasing temperature (Ea<0.1 eV). The effective mobility μ = R H/ρ at room temperature ranges from 0.02 to 1 cm 2/V·sec; it increases strongly with increasing Cr content, and decreases with increasing temperature. Small temperature coefficients of resistivity are obtained for the 25% Cr samples, where the temperature dependence of the carrier concentration cancels that of the mobility. Unannealed silicon-chromium films have hole concentrations a factor of 2-20 higher, depending on the composition and the sputtering voltage. The mobility of unannealed films is lower by a factor of 1.2-20. As a result, annealing increases the resistivity of some films (those sputtered at 2.5 kV) and decreases it for others (those sputtered at 1.0 kV). Annealing takes place between 400°and 600°C. The low values obtained for the effective mobility are in contradiction with a basic assumption of the free carrier model. Conduction mechanisms which could account for these low values are discussed. © 1969 The American Institute of Physics.