1/F NOISE IN GATE-CONTROLLED PLANAR SILICON DIODES

被引：9

作者：

LEUENBERGER, F

机构：

[1] Centre Electronique Horloger S.A., Neuchâtel

来源：

ELECTRONICS LETTERS | 1968年 / 4卷 / 13期

关键词：

D O I：

10.1049/el:19680215

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Low-frequency excess noise in planar bipolar silicon devices was investigated by means of gate-controlled n+-p diodes. Within the range of parameter values covered in this investigation, it was found that the noise-power maxima invariably occur at gate bias voltages leading to depletion of majority carriers at the surface of the high-resistivity side of the p-n junction. © 1968, The Institution of Electrical Engineers. All rights reserved.

引用

页码：280 / +

页数：1