A 320-MFLOPS CMOS FLOATING-POINT PROCESSING UNIT FOR SUPERSCALAR PROCESSORS

A CMOS pipelined floating-point processing unit (FPU) for superscalar processors is described. It is fabricated using a 0.5-mum CMOS triple-metal layer technology on a 61-mm2 die. The FPU has two execution modes to meet precise scientific computations and real-time applications. It can start two FPU operations in each cycle, and this achieves a peak performance of 160 MFLOPS double or single precision with an 80-MHz clock. Furthermore, the original computation mode, twin single-precision computation, doubles the peak performance and delivers 320-MFLOPS single precision. Its full bypass reduces the latency of operations, including load and store, and achieves an effective throughput even in nonvectorizable computations. An out-of-order completion is provided by using a new exception prediction method and a pipeline stall technique.