HIGH-PERFORMANCE SUBQUARTER-MICROMETER GATE CMOS TECHNOLOGY

被引:12
作者
OKAZAKI, Y
KOBAYASHI, T
MIYAKE, M
MATSUDA, T
SAKUMA, K
KAWAI, Y
TAKAHASHI, M
KANISAWA, K
机构
[1] NTT LSI Laboratories, Atsugi-shi, Kanagawa 243-01, 3-1 Morinosato, Wakamiya
关键词
D O I
10.1109/55.61787
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Subquarter-micrometer gate-length CMOS devices have been designed and fabricated. A single phosphorous-doped poly(n+)-Si gate and a 3.5-nm-thick gate oxide are used, and a retrograde twin-well structure with trench isolation has been adopted. Latch-up holding voltages exceed 8 V. The transconductances of 0.22-μm gate-length n and p MOSFET's are 450 and 330 mS/mm, and unloaded ring oscillator delays are 36 ps at 2 V. A static-type 1/2 divider that has nMOSFET's of 0.16-μm gate length and pMOSFET's of 0.22-μm gate length achieved a maximum operating frequency of 1.3 GHz and power of 5.6 mW at a supply voltage of 2 V. © 1990 IEEE
引用
收藏
页码:134 / 136
页数:3
相关论文
共 8 条
[1]  
Davari B., 1988, International Electron Devices Meeting. Technical Digest (IEEE Cat. No.88CH2528-8), P56, DOI 10.1109/IEDM.1988.32749
[2]   A NOVEL HIGH-SPEED NANOMETRIC ELECTRON-BEAM LITHOGRAPHY SYSTEM - EB-F [J].
IWADATE, K ;
YAMAGUCHI, R ;
HIRATA, K ;
HARADA, K .
JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B, 1987, 5 (01) :75-78
[3]  
KASAI N, 1987, IEDM TECH DIG, P367
[4]  
Kobayashi T., 1988, International Electron Devices Meeting. Technical Digest (IEEE Cat. No.88CH2528-8), P881, DOI 10.1109/IEDM.1988.32951
[5]   SUBQUARTER-MICROMETER GATE-LENGTH P-CHANNEL AND N-CHANNEL MOSFETS WITH EXTREMELY SHALLOW SOURCE-DRAIN JUNCTIONS [J].
MIYAKE, M ;
KOBAYASHI, T ;
OKAZAKI, Y .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1989, 36 (02) :392-398
[6]  
MIYAKE M, 1987 S VLSI TECHN DI, P91
[7]  
OKAZAKI Y, 1989 S VLSI TECHN DI, P13
[8]   MEV-ENERGY AS+ IMPLANTATION INTO SI - EXTENDED-DEFECT REDUCTION AND PLANAR N-P-N TRANSISTOR FABRICATION [J].
TAKAHASHI, M ;
KONAKA, S ;
KAJIYAMA, K .
JOURNAL OF APPLIED PHYSICS, 1983, 54 (10) :6041-6043