TIMING OPTIMIZATION OF MULTIPHASE SEQUENTIAL LOGIC

High-performance MOS circuits are frequently designed using precharged and dynamic logic. This requires the use of multiple phases of the system clock to ensure that the circuitry is precharged and refreshed at the proper times during each clock cycle. Finite state machines (FSM’s) used to control this type of logic must, therefore, be constructed as multiphase sequential logic with inputs and outputs stable during the appropriate phases. The timing optimization of multiphase logic entails the reduction of the overall cycle time of the machine and/or input to output delays by distributing computation throughout the entire clock cycle. We have developed a tool to automatically perform this optimization task and have implemented it as a set of extensions to the combinational logic optimization tool, misII. Our algorithms yield improvements that are on average 10-20% better than what is achievable using purely combinational logic optimization tools that do not move logic across latches. These improvements represent 75% of what would be possible in the most idealized case. Results on simple two-phase circuits show average input to output delay improvements of 13% with area penalties of 11%. For a four-phase controller used in the SPUR processor it yields an improvement in cycle time of 18% with an area penalty of 11%. Furthermore, our experiments indicate that the optimization algorithm is highly insensitive to parameter variations in the underlying combinational logic optimization routines and initial state assignment. © 1991 IEEE