HIGH SAMPLE RATE ARRAY ARCHITECTURES FOR MEDIAN FILTERS

被引：16

作者：

CHAKRABARTI, C

机构：

[1] Department of Electrical Engineering, Center for Telecommunications Research, Arizona State University, Tempe

来源：

IEEE TRANSACTIONS ON SIGNAL PROCESSING | 1994年 / 42卷 / 03期

关键词：

D O I：

10.1109/78.277872

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This correspondence presents high sample rate semi-systolic array architectures for computing 1-D and 2-D nonrecursive and recursive median filters. A high sample rate is obtained by pipelining the computations in each processor. Although the nonrecursive filters are pipelined by placing latches in the feedforward paths, the recursive filters are restructured to create additional delays in the feedback paths, and then pipelined using the delays as latches.

引用

页码：707 / 712

页数：6

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