PERFORMANCE, WIREABILITY, AND COOLING TRADEOFFS FOR PLANAR AND 3-D PACKAGING ARCHITECTURES

被引:4
作者
GEORGE, G
KRUSIUS, JP
机构
[1] School of Electrical Engineering, Cornell University, Ithaca, NY
来源
IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY PART B-ADVANCED PACKAGING | 1995年 / 18卷 / 02期
关键词
D O I
10.1109/96.386271
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Models for wiring length, cooling, wireability, and signal distribution are derived and integrated into a system-level performance metric used to compare packaging architectures for digital electronic systems. These include the common planar and stack-of-plane structures, in addition to fully 3-D structures with variable aspect ratios. This performance metric has been used to examine optimum packaging architectures for air and water-cooled systems as a function of a number of parameters including the total circuit count, The results show that none of these packaging architectures is always optimal. Rather, the optimum structure is determined by the specific set of system conditions chosen. The reader may easily use this model in order to determine the ''best'' packaging architecture for system parameters not included in this paper.
引用
收藏
页码:339 / 345
页数:7
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