3RD-ORDER CASCADED SIGMA-DELTA MODULATORS

In sigma-delta modulators, oversampling and negative feedback are used to shape the spectrum of the quantization noise, moving most of the noise energy to frequencies above the signal baseband. For a given oversampling ratio, the resolution of a sigma-delta modulator can be increased by increasing the order of the noise shaping. This can be accomplished, without concern for stability, by cascading several modulator stages, each of which combines a single quantizer with first- or second-order noise shaping. This paper explores a third-order cascaded sigma-delta modulator architecture wherein third-order noise shaping is achieved with relatively modest constraints on device matching. The architecture is based on a cascade of a second-order modulator stage followed by a first-order stage, both employing one-bit quantization. To improve the dynamic range, the input to the second stage is generated as an asymmetrically weighted error signal from the first stage. An analytical model for assessing the performance and device matching requirements of cascaded architectures is introduced, and computer simulations are used to verify the approximations made in this model. The analytical model is used to show that the proposed architecture offers performance comparable to other third-order cascaded sigma-delta modulator topologies, while being less sensitive to device matching errors.