ASSOCIATIVE MEMORIES AND PROCESSORS - OVERVIEW AND SELECTED BIBLIOGRAPHY

被引：42

作者：

PARHAMI, B ^{[1
]}

机构：

[1] UNIV CALIF, COMP SCI DEPT, LOS ANGELES, CA 90024 USA

来源：

PROCEEDINGS OF THE IEEE | 1973年 / 61卷 / 06期

关键词：

D O I：

10.1109/PROC.1973.9152

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：722 / 730

页数：9

共 175 条

[1] CALCULATIONS OF SPEED OF LADDER NETWORK FOR SUPERCONDUCTIVE ASSOCIATIVE MEMORIES [J].

AHRONS, RW .

IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS, 1965, EC14 (02) :267-&

[2]

AHRONS RW, 1963, RCA REV, V24, P325

[3]

APICELLA A, 1965, APR INT C MAGN

[4]

ASH WL, 1968, ACM NAT C P, P143

[5]

ASPINALL D, 1968, INFORM PROCESS

[6]

ATKIN J, 1962, IRE T EC, V11, P181

[7] STRUCTURE OF CRYOGENIC ASSOCIATIVE PROCESSOR [J].

BARNARD, JD ;

SEEBER, RR ;

BEHNKE, FA ;

LINDQUIST, AB .

PROCEEDINGS OF THE IEEE, 1964, 52 (10) :1182-&

[8] ILLIAC 4 COMPUTER [J].

BARNES, GH ;

BROWN, RM ;

KATO, M ;

KUCK, DJ ;

SLOTNICK, DL ;

STOKES, RA .

IEEE TRANSACTIONS ON COMPUTERS, 1968, C 17 (08) :746-&

[9]

BARTLETT J, 1970, ELECTRONICS AUG, P96

[10]

BATCHER KE, 1972, WESCON TECH PAPERS

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