IIR SWITCHED-CAPACITOR DECIMATOR BUILDING-BLOCKS WITH OPTIMUM IMPLEMENTATION

The concepts of multirate sampled-data signal processing play an important role in the area of multirate switched-capacitor (SC systems, i.e. systems that operate with more than one sampling rate. In such systems, the purpose of SC decimator building blocks is to reduce the sampling rate of a sampled-data signal from a high value MFS to a lower value F,. This paper is concerned with the design of SC decimators whose transfer functions have infinite impulse response (IIR). New optimum architectures are developed such that the speed requirements of the amplifiers are determined by the lower sampling rate Fs, thus rendering the circuits particularly attractive for high-frequency applications. Appropriate Z-transfer functions are derived for first- and second-order IIR SC decimator building blocks. Design examples of optimum IIR SC decimators with different types of frequency response, as well as different factors M of sampling rate reduction, are presented to demonstrate their practical feasibility. © 1990 IEEE