A BIT-SERIAL VLSI ARRAY-PROCESSING CHIP FOR IMAGE-PROCESSING

被引：8

作者：

HEATON, R ^{[1
]}

BLEVINS, D ^{[1
]}

DAVIS, E ^{[1
]}

机构：

[1] N CAROLINA STATE UNIV,DEPT COMP SCI,RALEIGH,NC 27695

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1990年 / 25卷 / 02期

关键词：

D O I：

10.1109/4.52157

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An array processing chip has been developed integrating 128 bit-serial processing elements (PE‘s) on a single die. Each PE has a 16-function logic unit, a single-bit adder, a 32-b variable-length shift register, and 1 kb of local RAM. Logic in each PE provides the capability to individually mask PE's. A modified grid interconnection scheme allows each PE to comniunicate to each of its eight nearest neighbors. A 32-b bus is used to transfer data to and from the array in a single cycle. Instruction execution is pipelined, enabling all instructions to be executed in a single cycle. The 1µm CMOS design contains over 1.1 million transistors on an 11.0-mm × 11.7-mm die. © 1990 IEEE

引用

页码：364 / 368

页数：5