INTEGRATED FRAMEWORK FOR YIELD MANAGEMENT AND DEFECT FAULT REDUCTION

被引：23

作者：

WEBER, C

MOSLEHI, B

DUTTA, M

机构：

[1] Technology Development Center, Integrated Circuits Business Division, Hewlett-Packard Company, Palo Alto, CA

来源：

IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING | 1995年 / 8卷 / 02期

关键词：

D O I：

10.1109/66.382274

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

An integrated framework for yield management and defect/fault reduction is presented. A 3-D space consisting of a quality axis, a process integration axis, and a scaling axis encompasses all process and manufacturing parameters. Crossfunctional teams of process, equipment, operations, and materials personnel proactively explore this space, and provide process engineers with a stable and capable environment for process development and manufacturing activities.

引用

页码：110 / 120

页数：11

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