A FULLY ASYNCHRONOUS DIGITAL SIGNAL PROCESSOR USING SELF-TIMED CIRCUITS

被引：22

作者：

JACOBS, GM

BRODERSEN, RW

机构：

[1] Department of Electrical Engineering and Computer Science, University of California, Berkeley, CA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1990年 / 25卷 / 06期

关键词：

D O I：

10.1109/4.62189

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A complete microprocessor-based digital signal processor (DSP) was designed and fabricated using self-timed circuits following a four-cycle handshake protocol to provide fully asynchronous operation without the need for any global clock. The general-purpose DSP, designed in 2-pm n-well CMOS, has an active area of 6.6 mm ×4.7 mm and instruction times range from 73 to 337 ns at 5 V, depending on the hardware requirements of each operation. © 1990 IEEE

引用

页码：1526 / 1537

页数：12

共 16 条

[1]

BAKOGLU H, 1986, THESIS STANFORD U ST

[2]

CHU TA, 1987, P ICCD

[3]

Erdelyi C. K., 1984, VLSI Design, V5, P78

[4] SAMPLE-SET DIFFERENTIAL LOGIC (SSDL) FOR COMPLEX HIGH-SPEED VLSI [J].

GROTJOHN, TA ;

HOEFFLINGER, B .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1986, 21 (02) :367-369

[5]

HELLER LG, 1984, FEB P INT SOL STAT C, P16

[6]

JACOBS G, 1988, VLSI SIGNAL PROCESSI, V3

[7]

JACOBS GM, 1988, 1988 IEEE VLSI WORKS

[8]

KOMORI S, 1989, FEB ISSCC

[9] IMPLEMENTATION OF ITERATIVE NETWORKS WITH CMOS DIFFERENTIAL LOGIC [J].

LU, SL .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1988, 23 (04) :1013-1017

[10]

MARTIN AJ, 1989, ADV RES VLSI

← 1 2 →