A 5-V-ONLY OPERATION 0.6-MU-M FLASH EEPROM WITH ROW DECODER SCHEME IN TRIPLE-WELL STRUCTURE

被引：108

作者：

UMEZAWA, A ^{[1
]}

ATSUMI, S ^{[1
]}

KURIYAMA, M ^{[1
]}

BANBA, H ^{[1
]}

IMAMIYA, K ^{[1
]}

NARUKE, K ^{[1
]}

YAMADA, S ^{[1
]}

OBI, E ^{[1
]}

OSHIKIRI, M ^{[1
]}

SUZUKI, T ^{[1
]}

TANAKA, S ^{[1
]}

机构：

[1] TOSHIBA MICROELECTR CORP,KAWASAKI 210,JAPAN

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1992年 / 27卷 / 11期

关键词：

D O I：

10.1109/4.165334

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An experimental 4-Mb flash EEPROM has been developed based on 0.6-mum triple-well CMOS technology in order to establish circuit technology for high-density flash memories. The possibility of achieving a cell size of 2.0 x 1.8 mum2 has been found by employing a negative-gate-biased source erase scheme and a self-aligned source (SAS) process technology. A newly developed row decoder with a triple-well structure has been realized in accordance with its small cell size. The source voltage during the erase operation was reduced by applying a negative voltage to the word line, which results in a 5-V-only operation. The chip size of the 4-Mb flash EEPROM is 8.11 x 6.95 mm2, and the estimated chip size of a 16-Mb flash EEPROM is 98.4 mm2 by employing the minimal cell size (2.0 x 1.8 mum2).

引用

页码：1540 / 1546

页数：7