SYNTHESIS OF HAZARD-FREE ASYNCHRONOUS CIRCUITS WITH BOUNDED WIRE DELAYS

This paper introduces a new synthesis methodology for asynchronous sequential control circuits from a high level specification, the Signal Transition Graph (STG). The methodology is guaranteed to generate hazard-free circuits with the bounded wire-delay model, if the STG is live and has the Complete State Coding property. The methodology exploits knowledge of the environmental delays, speed-independence with respect to externally visible signals, and logic synthesis techniques. A proof that STG persistency is neither necessary nor sufficient for hazard-free implementation is given.