CMOS CIRCUIT SPEED AND BUFFER OPTIMIZATION

An improved timing model for CMOS combinational logic is presented. The model is based on an analytical solution for the CMOS inverter output response to an input ramp. This model yields a better understanding of the switching behavior of the CMOS inverter than the step-response model by considering the slope of the input waveform. As an example, the timing model is used to optimize CMOS output buffers for minimum delay. If the intrinsic output load capacitance is included in the model, the optimum tapering factor is shown to be not e but a value in the range of 3-5 depending on process parameters and design style. Also, due to the input dependence of the propagation delay, the last inverter stage in the buffer should have a larger tapering factor than the other stages for minimum delay.